24 {
"GAIN_CONV",
Parameter(0, 4, 4, 0b0100)},
27 {
"DACB_VB_CONV",
Parameter(1, 2, 6, 0b110011)},
30 {
"DACB_VBI_PA",
Parameter(2, 2, 6, 0b011111)},
34 {
"IBO_INV",
Parameter(4, 2, 6, 0b001010)},
36 {
"IBO_NOINV",
Parameter(5, 2, 6, 0b001010)},
37 {
"IBI_INV_BUF",
Parameter(6, 0, 2, 0b11)},
38 {
"IBO_INV_BUF",
Parameter(6, 2, 6, 0b100110)},
39 {
"IBI_NOINV_BUF",
Parameter(7, 0, 2, 0b11)},
40 {
"IBO_NOINV_BUF",
Parameter(7, 2, 6, 0b100110)},
43 {
"SW_CF_COMP",
Parameter(8, 4, 4, 0b1010)},
46 {
"CLR_SHAPERTAIL",
Parameter(10, 1, 1, 0)},
47 {
"SELRISINGEDGE",
Parameter(10, 2, 1, 1)},
53 {
"S_INV_BUF",
Parameter(12, 2, 3, 0b110)},
54 {
"S_NOINV_BUF",
Parameter(12, 5, 3, 0b110)},
68 {{
"PROBE_VREF_PA",
Parameter(0, 0, 1, 0)},
69 {
"PROBE_VREF_TIME",
Parameter(0, 1, 1, 0)},
96 {{
"GLOBAL_TA_SELECT_GAIN_TOA",
Parameter(0, 0, 4, 0b0011)},
97 {
"GLOBAL_TA_SELECT_GAIN_TOT",
Parameter(0, 4, 4, 0b0011)},
98 {
"GLOBAL_MODE_NO_TOT_SUB",
Parameter(1, 0, 1, 0)},
99 {
"GLOBAL_LATENCY_TIME",
Parameter(1, 1, 4, 0b1010)},
100 {
"GLOBAL_MODE_FTDC_TOA_S0",
Parameter(1, 5, 1, 0)},
101 {
"GLOBAL_MODE_FTDC_TOA_S1",
Parameter(1, 6, 1, 1)},
102 {
"GLOBAL_SEU_TIME_OUT",
Parameter(1, 7, 1, 1)},
103 {
"BIAS_FOLLOWER_CAL_P_D",
Parameter(2, 0, 4, 0)},
104 {
"BIAS_FOLLOWER_CAL_P_EN",
Parameter(2, 4, 1, 0)},
105 {
"INV_FRONT_40MHZ",
Parameter(2, 5, 1, 0)},
106 {
"START_COUNTER",
Parameter(2, 6, 1, 1)},
107 {
"CALIB_CHANNEL_DLL",
Parameter(2, 7, 1, 0)},
109 {
"VD_CTDC_P_DAC_EN",
Parameter(3, 5, 1, 0)},
110 {
"EN_MASTER_CTDC_VOUT_INIT",
Parameter(3, 6, 1, 0)},
111 {
"EN_MASTER_CTDC_DLL",
Parameter(3, 7, 1, 1)},
112 {
"BIAS_CAL_DAC_CTDC_P_D",
115 {
"CTDC_CALIB_FREQUENCY",
Parameter(4, 2, 6, 0b000010)},
116 {
"GLOBAL_MODE_TOA_DIRECT_OUTPUT",
Parameter(5, 0, 1, 0)},
117 {
"BIAS_I_CTDC_D",
Parameter(5, 1, 6, 0b011000)},
118 {
"FOLLOWER_CTDC_EN",
Parameter(5, 7, 1, 1)},
119 {
"GLOBAL_EN_BUFFER_CTDC",
Parameter(6, 0, 1, 0)},
120 {
"VD_CTDC_N_FORCE_MAX",
Parameter(6, 1, 1, 1)},
122 {
"VD_CTDC_N_DAC_EN",
Parameter(6, 7, 1, 0)},
123 {
"CTRL_IN_REF_CTDC_P_D",
Parameter(7, 0, 5, 0)},
124 {
"CTRL_IN_REF_CTDC_P_EN",
Parameter(7, 5, 1, 0)},
125 {
"CTRL_IN_SIG_CTDC_P_D",
Parameter(8, 0, 5, 0)},
126 {
"CTRL_IN_SIG_CTDC_P_EN",
Parameter(8, 5, 1, 0)},
127 {
"GLOBAL_INIT_DAC_B_CTDC",
Parameter(8, 6, 1, 0)},
128 {
"BIAS_CAL_DAC_CTDC_P_EN",
Parameter(8, 7, 1, 0)},
130 {
"VD_FTDC_P_DAC_EN",
Parameter(9, 5, 1, 0)},
131 {
"EN_MASTER_FTDC_VOUT_INIT",
Parameter(9, 6, 1, 0)},
132 {
"EN_MASTER_FTDC_DLL",
Parameter(9, 7, 1, 1)},
133 {
"BIAS_CAL_DAC_FTDC_P_D",
136 {
"FTDC_CALIB_FREQUENCY",
Parameter(10, 2, 6, 0b000010)},
138 {
"BIAS_I_FTDC_D",
Parameter(11, 1, 6, 0b011000)},
139 {
"FOLLOWER_FTDC_EN",
Parameter(11, 7, 1, 1)},
140 {
"GLOBAL_EN_BUFFER_FTDC",
Parameter(12, 0, 1, 0)},
141 {
"VD_FTDC_N_FORCE_MAX",
Parameter(12, 1, 1, 1)},
143 {
"VD_FTDC_N_DAC_EN",
Parameter(12, 7, 1, 0)},
144 {
"CTRL_IN_SIG_FTDC_P_D",
Parameter(13, 0, 5, 0)},
145 {
"CTRL_IN_SIG_FTDC_P_EN",
Parameter(13, 5, 1, 0)},
146 {
"GLOBAL_INIT_DAC_B_FTDC",
Parameter(13, 6, 1, 0)},
147 {
"BIAS_CAL_DAC_FTDC_P_EN",
Parameter(13, 7, 1, 0)},
148 {
"CTRL_IN_REF_FTDC_P_D",
Parameter(14, 0, 5, 0)},
149 {
"CTRL_IN_REF_FTDC_P_EN",
Parameter(14, 5, 1, 0)},
150 {
"GLOBAL_DISABLE_TOT_LIMIT",
Parameter(15, 0, 1, 0)},
151 {
"GLOBAL_FORCE_EN_CLK",
Parameter(15, 1, 1, 0)},
152 {
"GLOBAL_FORCE_EN_OUTPUT_DATA",
Parameter(15, 2, 1, 0)},
153 {
"GLOBAL_FORCE_EN_TOT",
Parameter(15, 3, 1, 0)}});
160 {{
"INPUTDAC",
Parameter(0, 0, 6, 0b011111)},
170 {
"SEL_TRIGGER_TOA",
Parameter(3, 6, 1, 0)},
176 {
"SEL_TRIGGER_TOT",
Parameter(4, 4, 1, 0)},
180 {
"DAC_CAL_FTDC_TOA",
Parameter(5, 0, 6, 0)},
182 {
"DAC_CAL_CTDC_TOA",
Parameter(6, 0, 6, 0)},
183 {
"DAC_CAL_FTDC_TOT",
Parameter(7, 0, 6, 0)},
184 {
"DAC_CAL_CTDC_TOT",
Parameter(8, 0, 6, 0)},
185 {
"IN_FTDC_ENCODER_TOA",
Parameter(9, 0, 6, 0)},
186 {
"IN_FTDC_ENCODER_TOT",
Parameter(10, 0, 6, 0)},
190 {
"MASK_ALIGNBUFFER",
Parameter(11, 7, 1, 0)},
191 {
"ADC_PEDESTAL",
Parameter(12, 0, 8, 0)}});
202 {
"MULTFACTOR",
Parameter(1, 0, 5, 0b11001)},
209 0b1100110011001100110011001100)},
228 {
"ERROR_LIMIT_SC",
Parameter(0, 1, 3, 0b010)},
229 {
"SEL_PLL_LOCKED",
Parameter(0, 4, 1, 1)},
237 {
"VOUT_INIT_EXT_EN",
Parameter(2, 0, 1, 0)},
238 {
"VOUT_INIT_EXT_D",
Parameter(2, 1, 5, 0)},
239 {
"FOLLOWER_PLL_EN",
Parameter(3, 0, 1, 1)},
240 {
"BIAS_I_PLL_D",
Parameter(3, 1, 6, 0b011000)},
242 {
"PLL_PROBE_AMPLITUDE",
Parameter(4, 0, 3, 0b011)},
243 {
"PLL_PROBE_PRE_SCALE",
Parameter(4, 3, 3, 0)},
244 {
"PLL_PROBE_PRE_PHASE",
Parameter(4, 6, 2, 0)},
245 {
"ET_AMPLITUDE",
Parameter(5, 0, 3, 0b011)},
248 {
"SEL_RESYNC_FCMD",
Parameter(6, 0, 1, 1)},
250 {
"SEL_STROBE_FCMD",
Parameter(6, 2, 1, 1)},
251 {
"SEL_ORBITSYNC_FCMD",
Parameter(6, 3, 1, 1)},
252 {
"EN_PHASESHIFT",
Parameter(7, 0, 1, 1)},
forward declare register map LUT types
Definition register_maps_types.h:96
Header defining types stored within the parameter to register mappings.
const Page TOP_LUT
The Look Up Table of for the Top sub-block of an HGC ROC.
Definition sipm_rocv2.h:226
const ParameterLUT PARAMETER_LUT
Entire parameter Look Up Table.
Definition sipm_rocv2.h:267
const Page GLOBAL_ANALOG_LUT
The Look Up Table of for the Global Analog sub-blocks of an HGC ROC.
Definition sipm_rocv2.h:19
const Page MASTER_TDC_LUT
The Look Up Table of for the Master TDC sub-blocks` of an HGC ROC.
Definition sipm_rocv2.h:95
const Page DIGITAL_HALF_LUT
The Look Up Table of for the Digital Half sub-blocks` of an HGC ROC.
Definition sipm_rocv2.h:197
const Page CHANNEL_WISE_LUT
The Look Up Table of for the individual channel sub-blocks` of an HGC ROC.
Definition sipm_rocv2.h:159
const Page REFERENCE_VOLTAGE_LUT
The Look Up Table of for the Reference Voltage sub-blocks of an HGC ROC.
Definition sipm_rocv2.h:67
A parameter for the HGC ROC includes one or more register locations and a default value defined in th...
Definition register_maps_types.h:47
Structure holding a location in the registers.
Definition register_maps_types.h:23