daq.cxx File Reference

DAQ menu (and submenus) command definitions. More...

#include "daq_run.h"
#include "pflib/packing/Hex.h"
#include "pflib/utility/string_format.h"
#include "pftool.h"

Include dependency graph for daq.cxx:

Functions
	ENABLE_LOGGING ()
static void	print_daq_status (Target *pft)
static void	daq_setup (const std::string &cmd, Target *pft)
	DAQ->SETUP menu commands.
static void	daq_setup_standard (Target *tgt)
	DAQ.SETUP.STANDARD.
static void	daq (const std::string &cmd, Target *pft)
	DAQ menu commands, DOES NOT include sub-menu commands.
static void	daq_debug_trigger_timein (Target *tgt)
	DAQ.DEBUG.TRIGGER_TIMEIN.

Detailed Description

DAQ menu (and submenus) command definitions.

Function Documentation

daq()

static void daq ( const std::string & cmd, Target * pft )

static

DAQ menu commands, DOES NOT include sub-menu commands.

Commands

• RESET : pflib::DAQ::reset
• READ : pflib::Target::daqReadDirect with option to save output to file
• PEDESTAL : pflib::Target::prepareNewRun and then send an L1A trigger with pflib::Backend::fc_sendL1A and collect events with pflib::Target::daqReadEvent for the input number of events
• CHARGE : same as PEDESTAL but using pflib::Backend::fc_calibpulse instead of direct L1A
• SCAN : do a PEDESTAL (or CHARGE)-equivalent for each value of an input parameter with an input min, max, and step

Parameters

[in]	cmd	command selected from menu
[in]	pft	active target

daq_debug_trigger_timein()

static void daq_debug_trigger_timein ( Target * tgt )

static

DAQ.DEBUG.TRIGGER_TIMEIN.

This command attempts to deduce the capture delay for the trigger links by taking two runs after setting some parameters on the chip.

Assuming the pedestal values on the chip are all ~200 (as is the case at UMN), setting the CH_XX.ADC_PEDESTAL and DIGITALHALF_X.ADC_TH to their maxima (255 and 31 respectively) forces the trigger sums to be zero for pedestals. Including the 4-bit sync header, this means the trigger link zero-word is 0xa0000000.

We then enable charge injection within certain channels. Each trigger link produces a single 32-bit word cut up into a 4-bit sync header and 4 7-bit trigger sums.

0b1010 | TCX_0 | TCX_1 | TCX_2 | TCX_3

We choose channels to inject charge such that each link has a different trigger sum that should be non-zero.

• CH_0 -> TC0_0 non-zero
• CH_29 -> TC1_2 non-zero
• CH_42 -> TC2_1 non-zero
• CH_70 -> TC3_3 non-zero

The window size in the firmware is stored in 6 bits, so the maximum capture window (and therefore maximum delay) is 63 (2^6 - 1).

Note

Capture windows larger than 63 seem to be naively trimmed without warning or notice.

The pedestal run producing trigger-zero words filters out words that can be captured by this link but "belong" to a different link. We can then check which words are different between the charge and pedestal runs, printing the word indices (delays) for them. The last step is checking if the word from the charge run is zero everywhere except the expected bits.

Finally, report the delays where we found the expected bits to be non-zero

daq_setup()

static void daq_setup ( const std::string & cmd, Target * pft )

static

DAQ->SETUP menu commands.

Before doing any of the commands, we retrieve a reference to the daq object via pflib::Target::daq.

Commands

• ENABLE : toggle whether daq is enabled pflib::DAQ::enable and pflib::DAQ::enabled
• ZS : pflib::Target::enableZeroSuppression
• L1APARAMS : Use target's wishbone interface to set the L1A delay and capture length Uses pflib::tgt_DAQ_Inbuffer
• FORMAT : Choose the output format to be used (simple HGCROC, ECON, etc)
• DMA : enable DMA readout pflib::rogue::RogueWishboneInterface::daq_dma_enable
• FPGA : Set the polarfire FPGA ID number (pflib::DAQ::setIds) and pass this to DMA setup if it is enabled

Parameters

[in]	cmd	selected command from DAQ->SETUP menu
[in]	pft	active target

daq_setup_standard()

static void daq_setup_standard ( Target * tgt )

static

DAQ.SETUP.STANDARD.

Do the standard setup for the HGCROC (i.e. the setup everyone should use unless you are looking at changing L1OFFSET or fast control command timing).

What Do

• Setup fast control so that the calib-pulse and l1a are timed in and the trigger links are delayed slightly so we can gather a pre-sample (see Issue #140 and PR #151 for context)
• Configure ROC to have L1OFFSET corresponding to this FC timing
• Put ROC into Running Mode
• Set delays and captures on the elinks

When to Call

This command is designed to set up this configuration on other (non software memory) places so that it does not need to be called often. Specifically, we store things in

• the firmware's memory block via UIO for link capture and fast command settings
• the HGCROC's parameter registers This means if either the firmware is reset/reloaded or the HGCROC is reset/power-cycled, this function needs to be called.

Note

If the firmware was changed or the HGCROC was power-cycled, make sure to align the elinks before calling this function (e.g. with EXPERT.ELINKS.AUTO which has been pretty stable).

do a standard fast control setup before tuning it below

In order to be able to shift the trigger link delay away from zero and allow us to capture a pre-sample in the trigger path, we need to bring the L1A closer in time to the injected charge pulse.

this then requires us to lower the L1OFFSET as well

Note

only correct right now for the single-board readout

DAQ link, timed in with pedestals and idles

Trigger link, timed in with DAQ.DEBUG.TRIGGER_TIMEIN

There is only one word per crossing per trigger link, but we capture four (one pre-sample and 2 following samples).