EcalRawEncoder.cxx

#include "Ecal/EcalRawEncoder.h"
 
#include <bitset>
 
#include "DetDescr/EcalElectronicsID.h"
#include "DetDescr/EcalID.h"
#include "Ecal/EcalDetectorMap.h"
#include "Packing/Utility/BufferReader.h"
#include "Packing/Utility/CRC.h"
#include "Packing/Utility/Mask.h"
#include "Recon/Event/HgcrocDigiCollection.h"
 
namespace ecal {
 
EcalRawEncoder::EcalRawEncoder(const std::string& name,
                               framework::Process& process)
    : Producer(name, process) {}
 
EcalRawEncoder::~EcalRawEncoder() {}
 
void EcalRawEncoder::configure(framework::config::Parameters& ps) {
  input_name_ = ps.getParameter<std::string>("input_name");
  input_pass_ = ps.getParameter<std::string>("input_pass");
  output_name_ = ps.getParameter<std::string>("output_name");
  roc_version_ = ps.getParameter<int>("roc_version");
}
 
void EcalRawEncoder::produce(framework::Event& event) {
  // static const unsigned int common_mode_channel = roc_version_ == 2 ? 19 : 1;
 
  auto digis{
      event.getObject<ldmx::HgcrocDigiCollection>(input_name_, input_pass_)};
  std::vector<std::map<
      uint16_t, std::map<uint16_t, std::map<uint32_t, uint32_t>  // channel to
                                                                 // sample
                         >                                       // links
      >                                                          // fpgas
              >                                                  // bunches
      sorted_samples(digis.getNumSamplesPerDigi());
 
  auto detmap{
      getCondition<EcalDetectorMap>(EcalDetectorMap::CONDITIONS_OBJECT_NAME)};
  for (auto digi : digis) {
    ldmx::EcalID detid{digi.id()};
    ldmx::EcalElectronicsID eid{detmap.get(detid)};
 
    for (std::size_t i_bx{0}; i_bx < digis.getNumSamplesPerDigi(); i_bx++) {
      sorted_samples[i_bx][eid.fiber()][eid.elink()][eid.channel()] =
          digi.at(i_bx).raw();
    }
  }
 
  std::vector<uint32_t> buffer;
  // word to use for constructing buffer
  static uint32_t word;
  uint32_t i_bx{0};
  for (auto const& bunch : sorted_samples) {
    uint32_t bunch_id = event.getEventNumber();
    uint32_t rreq = i_bx;
    uint32_t orbit = event.getEventHeader().getRun();
 
    // bunch lists the fpgs, links, and channels with their corresponding sample
    for (auto const& [fpga_id, links] : bunch) {
      std::vector<uint32_t> link_lengths;
      for (auto const& [link_id, channels] : links) {
        link_lengths.push_back(3 + 1 + channels.size() + 1);
      }
 
      uint32_t n_linkwords =
          link_lengths.size() / 4 + (link_lengths.size() % 4 != 0);
      uint32_t total_length{2 + n_linkwords + 1};
      for (uint32_t const& link_len : link_lengths) {
        total_length += link_len;
      }
 
      packing::utility::CRC fpga_crc;
      word = 0;
 
      word |= (1 << (12 + 1 + 6 + 8));                                // version
      word |= (fpga_id & packing::utility::mask<8>) << (12 + 1 + 6);  // FPGA
      word |= (links.size() & packing::utility::mask<6>) << (12 + 1);  // NLINKS
      word |= (total_length & packing::utility::mask<12>);  // LEN TODO
      buffer.push_back(word);
      fpga_crc << word;
 
      word = 0;
      word |= (bunch_id & packing::utility::mask<12>) << 20;  // BX ID
      word |= (rreq & packing::utility::mask<10>) << 10;      // RREQ
      word |= (orbit & packing::utility::mask<10>);           // OR
      buffer.push_back(word);
      fpga_crc << word;
 
      for (uint32_t i_linkword{0}; i_linkword < n_linkwords; i_linkword++) {
        word = 0;
        for (uint32_t i_linklen{0}; i_linklen < 4; i_linklen++) {
          uint32_t i_link = 4 * i_linkword + i_linklen;
          if (i_link <= link_lengths.size()) {
            // we have a link
            word |= (((0b11 << 6) +
                      (link_lengths.at(i_link) & packing::utility::mask<6>))
                     << 8 * i_linklen);
          }  // do we have a link for this linklen subword?
        }    // loop through subwords in this word
        buffer.push_back(word);
        fpga_crc << word;
      }  // loop through words
 
      // fpga lists the links and channels with their corresponding sample
      for (auto const& [link_id, channels] : links) {
        std::bitset<40> ro_map;  // starts as all 0s
        ro_map.set(0);           // special "header" word from ROC
        ro_map.set(39);          // trailing checksum from ROC
        // each link maps the channels that were readout to their sample
        for (auto const& [channel, sample] : channels) {
          ro_map.set(channel);
        }
 
        packing::utility::CRC link_crc;
        word = 0;
        word |= (link_id & packing::utility::mask<16>) << 16;
        word |= 1 << 15;
        // put first 8bits of RO Map in first header word
        word |= (ro_map >> 32).to_ulong();
 
        buffer.push_back(word);
        fpga_crc << word;
        link_crc << word;
 
        // next header word is end of RO map
        word = (ro_map.to_ulong() & 0xFFFFFFFF);
        buffer.push_back(word);
        fpga_crc << word;
        link_crc << word;
 
        // special "header" word from ROC
        word = 0;
        word |= 0b0101 << 28;
        word |= (bunch_id & packing::utility::mask<12>) << 16;
        word |= (rreq & packing::utility::mask<6>) << 10;
        word |= (orbit & packing::utility::mask<3>) << 7;
        // skipping hamming error bits because we will set them all to false
        // here
        word |= 0b0101;
        buffer.push_back(word);
        fpga_crc << word;
        link_crc << word;
 
        // put samples into buffer
        for (auto const& [channel, sample] : channels) {
          buffer.push_back(sample);
          fpga_crc << sample;
          link_crc << sample;
        }
        buffer.push_back(link_crc.get());
        fpga_crc << link_crc.get();
      }
    }
    i_bx++;
  }
 
  event.add(output_name_, buffer);
 
  return;
}  // produce
 
}  // namespace ecal
 
DECLARE_PRODUCER_NS(ecal, EcalRawEncoder);